ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Breakpoint enable, bit [0]
0b11 Match in any mode.
Debug Registers Reference
This field must be programmed to 0b11 if the DBGBVR meaning field, bits [22:20], is
programmed for Linked Context ID match.
This bit enables the BRP. The meaning of this bit is:
0 Breakpoint disabled
1 Breakpoint enabled.
A BRP never generates Breakpoint debug events when its DBGBCR is disabled.
The debug logic reset values of all bits of the DBGBCR are UNKNOWN.
Note
In v6 Debug and v6.1 Debug, the Breakpoint enable bit of the DBGBCR is set to 0 on a debug logic
reset, disabling the breakpoint.
In v7 Debug, a debugger must ensure that DBGBCR[0] has a defined state before it programs
DBGDSCR[15:14] to enable debug.
Byte address selection behavior on IVA match or mismatch
The DBGBVR is programmed with a word address. If you have programmed the BRP for Linked or
Unlinked IVA match or mismatch, you can program the Byte address select field, DBGBCR[8:5], so that
the breakpoint hits only if certain byte addresses are accessed. The exact interpretation depends on the
processor instruction set state, as indicated by the CPSR.J and CPSR.T bits, and on the bottom two bits of
the IVA. Table C10-11 on page C10-56 shows the operation of byte address masking using the
DBGBCR[8:5] field.
Note
In the following cases, you must program DBGBCR[8:5] to 0b1111:
if you program the BRP for Linked or Unlinked Context ID match
in v7 Debug, if you program the BRP for linked or unlinked IVA match or mismatch with a nonzero
Address range mask.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C10-55