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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Assembler syntax<br />

SMLAL , , , <br />

where:<br />

Instruction Details<br />

Specifies which half of the source register is used as the first multiply oper<strong>and</strong>. If <br />

is B, then the bottom half (bits [15:0]) of is used. If is T, then the top half<br />

(bits [31:16]) of is used.<br />

Specifies which half of the source register is used as the second multiply oper<strong>and</strong>. If<br />

is B, then the bottom half (bits [15:0]) of is used. If is T, then the top half<br />

(bits [31:16]) of is used.<br />

See St<strong>and</strong>ard assembler syntax fields on page A8-7.<br />

Supplies the lower 32 bits of the accumulate value, <strong>and</strong> is the destination register for the<br />

lower 32 bits of the result.<br />

Supplies the upper 32 bits of the accumulate value, <strong>and</strong> is the destination register for the<br />

upper 32 bits of the result.<br />

The source register whose bottom or top half (selected by ) is the first multiply oper<strong>and</strong>.<br />

The source register whose bottom or top half (selected by ) is the second multiply<br />

oper<strong>and</strong>.<br />

Operation<br />

if ConditionPassed() then<br />

EncodingSpecificOperations();<br />

oper<strong>and</strong>1 = if n_high then R[n] else R[n];<br />

oper<strong>and</strong>2 = if m_high then R[m] else R[m];<br />

result = SInt(oper<strong>and</strong>1) * SInt(oper<strong>and</strong>2) + SInt(R[dHi]:R[dLo]);<br />

R[dHi] = result;<br />

R[dLo] = result;<br />

Exceptions<br />

None.<br />

<strong>ARM</strong> DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. A8-337

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