ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
VADDL. , , Encoded as op = 0
VADDW. {,} , Encoded as op = 1
where:
Instruction Details
See Standard assembler syntax fields on page A8-7. An ARM VADDL or VADDW instruction
must be unconditional.
The data type for the elements of the second operand vector. It must be one of:
S8 encoded as size = 0b00, U = 0
S16 encoded as size = 0b01, U = 0
S32 encoded as size = 0b10, U = 0
U8 encoded as size = 0b00, U = 1
U16 encoded as size = 0b01, U = 1
U32 encoded as size = 0b10, U = 1.
The destination register. If this register is omitted in a VADDW instruction, it is the same
register as .
, The first and second operand registers for a VADDW instruction.
, The first and second operand registers for a VADDL instruction.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled();
for e = 0 to elements-1
if is_vaddw then
op1 = Int(Elem[Q[n>>1],e,2*esize], unsigned);
else
op1 = Int(Elem[D[n],e,esize], unsigned);
result = op1 + Int(Elem[D[m],e,esize],unsigned);
Elem[Q[d>>1],e,2*esize] = result;
Exceptions
Undefined Instruction.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-543