ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
TRE, bit [28] TEX Remap Enable bit. This bit enables remapping of the TEX[2:1] bits for use as two
translation table bits that can be managed by the operating system. Enabling this remapping
also changes the scheme used to describe the memory region attributes in the VMSA. The
possible values of this bit are:
0 TEX Remap disabled. TEX[2:0] are used, with the C and B bits, to describe the
memory region attributes.
1 TEX Remap enabled. TEX[2:1] are reassigned for use as flags managed by the
operating system. The TEX[0], C and B bits are used to describe the memory
region attributes, with the MMU remap registers.
When the Security Extensions are implemented, this bit is banked between the Secure and
Non-secure versions of the register.
For more information, see The alternative descriptions of the Memory region attributes on
page B3-32.
NMFI, bit [27]
Non-maskable Fast Interrupts enable:
0 Fast interrupts (FIQs) can be masked in the CPSR
1 Fast interrupts are non-maskable.
When the Security Extensions are implemented this bit is common to the Secure and
Non-secure versions of the register.
This bit is read-only. It is IMPLEMENTATION DEFINED whether an implementation supports
Non-Maskable Fast Interrupts (NMFIs):
If NMFIs are not supported then this bit must be RAZ.
If NMFIs are supported then this bit is controlled by a configuration input signal.
For more information, see Non-maskable fast interrupts on page B1-18.
Bit [26] RAZ/SBZP.
EE, bit [25] Exception Endianness bit. The value of this bit defines the value of the CPSR.E bit on entry
to an exception vector, including reset. This value also indicates the endianness of the
translation table data for translation table lookups. The permitted values of this bit are:
0 Little endian
1 Big endian.
When the Security Extensions are implemented, this bit is banked between the Secure and
Non-secure versions of the register.
This is a read/write bit. An implementation can include a configuration input signal that
determines the reset value of the EE bit. If there is no configuration input signal to determine
the reset value of this bit then it resets to 0.
VE, bit [24] Interrupt Vectors Enable bit. This bit controls the vectors used for the FIQ and IRQ
interrupts. The permitted values of this bit are:
0 Use the FIQ and IRQ vectors from the vector table, see the V bit entry
1 Use the IMPLEMENTATION DEFINED values for the FIQ and IRQ vectors.
B3-98 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B