ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

H.7.12 c9, TCM support
ARMv4 and ARMv5 Differences
TCM register support is optional when CP15 and TCM are supported in ARMv4 and ARMv5. For details
see c9, TCM support on page AppxG-46.
H.7.13 c10, VMSA TLB lockdown support
TLB lockdown is an optional feature that enables the results of specified translation table walks to load into
the TLB in a way that prevents them being overwritten by the results of subsequent translation table walks.
Translation table walks can take a long time because they involve potentially slow main memory accesses.
In real-time interrupt handlers, translation table walks caused by the TLB that do not contain translations
for the handler or the data it accesses can increase interrupt latency significantly.
Two basic lockdown models are supported:
a TLB lock by entry model
a translate and lock model introduced as an alternative model in ARMv5TE.
In an ARMv6 implementation that includes the Security Extensions, c10 TLB Lockdown registers are
Configurable access registers, with access controlled by the NSACR. For more information, see:
Configurable access CP15 registers on page B3-74 for general information
c1, Non-Secure Access Control Register (NSACR) on page B3-110 and c1, VMSA Security Extensions
support on page AppxG-35 for details of the NSACR.
From ARMv7, TLB lockdown is IMPLEMENTATION DEFINED with no recommended formats or mechanisms
on how it is achieved other than reserved CP15 register space. See TLB lockdown on page B3-56 and CP15
c10, Memory remapping and TLB control registers on page B3-142.
Table H-25 shows the TLB operations used to support the different mechanisms.
Table H-25 TLB lockdown register support
Register or operation Mechanism CRn opc1 CRm opc2
Data or unified TLB Lockdown Register, DTLBLR By entry c10 0 c0 a 0
Instruction TLB Lockdown Register, ITLBLR By entry c10 0 c0 a 1
Lock instruction TLB Translate and lock c10 0 c4 b 0
Unlock instruction TLB Translate and lock c10 0 c4 b 1
Lock data TLB Translate and lock c10 0 c8 b 0
Unlock data TLB Translate and lock c10 0 c8 b 1
a. Read/write register that can be accessed using MCR and MRC instructions.
b. Write-only operation that is accessed only using the MCR instruction.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. AppxH-59