ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
where:
Instruction Details
VABS. , != F64
VABS. ,
VABS.F32 , VFP only. Encoding T2/A2, sz = 0
See Standard assembler syntax fields on page A8-7. An ARM Advanced SIMD VABS
instruction must be unconditional.
The data type for the elements of the vectors. It must be one of:
S8 encoding T1 / A1, size = 0b00, F = 0
S16 encoding T1 / A1, size = 0b01, F = 0
S32 encoding T1 / A1, size = 0b10, F = 0
F32 encoding T1 / A1, size = 0b10, F = 1
F64 encoding T2 / A2, sz = 1.
, The destination vector and the operand vector, for a quadword operation.
, The destination vector and the operand vector, for a doubleword operation.
, The destination vector and the operand vector, for a singleword operation.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDOrVFPEnabled(TRUE, advsimd);
if advsimd then // Advanced SIMD instruction
for r = 0 to regs-1
for e = 0 to elements-1
if floating_point then
Elem[D[d+r],e,esize] = FPAbs(Elem[D[m+r],e,esize]);
else
result = Abs(SInt(Elem[D[m+r],e,esize]));
Elem[D[d+r],e,esize] = result;
else // VFP instruction
if dp_operation then
D[d] = FPAbs(D[m]);
else
S[d] = FPAbs(S[m]);
Exceptions
Undefined Instruction.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-533