ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
Cacheable memory attributes
When TEX[2] == 1, the translation table entry describes Cacheable memory, and the rest of the encoding
defines the Inner and Outer cache attributes:
TEX[1:0] defines the Outer cache attribute
C,B defines the Inner cache attribute
The same encoding is used for the Outer and Inner cache attributes. Table B3-8 shows the encoding.
B3.7.3 Memory region attribute descriptions when TEX remap is enabled
The VMSAv6 scheme for describing the memory region attributes, described in C, B, and TEX[2:0]
encodings without TEX remap on page B3-33, uses the TEX[2:0], C and B bits to describe all of the options
for Inner and Outer cacheability. However, many system software implementations do not need to use all of
these options simultaneously. Instead a smaller subset of attributes can be enabled. This alternative
functionality is called TEX remap, and permits software to hold software-interpreted values in the
translation tables. When TEX remap is enabled:
only the TEX[0], C and B bits are used to describe the memory region attributes
fewer attribute options are available at any time
the available options are configurable using the PRRR and NMRR registers
TEX[2:1] are not updated by hardware, see The OS managed translation table bits on page B3-38.
When TEX remap is enabled:
Table B3-8 Inner and Outer cache attribute encoding
Encoding Cache attribute
0 0 Non-cacheable
0 1 Write-Back, Write-Allocate
1 0 Write-Through, no Write-Allocate
1 1 Write-Back, no Write-Allocate
For seven of the eight possible combinations of the TEX[0], C and B bits:
— a field in the PRRR defines the corresponding memory region as being Normal, Device or
Strongly-ordered memory
— a field in the NMRR defines the Inner cache attributes that apply if the PRRR field identifies
the region as Normal memory
— a second field in the NMRR defines the Outer cache attributes that apply if the PRRR field
identifies the region as Normal memory.
The meaning of the eighth combination for the TEX[0], C and B bits is IMPLEMENTATION DEFINED
B3-34 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B