ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
Similar rules apply:
to cache behavior, see Behavior of the caches at reset on page B2-6
to branch predictor behavior, see Behavior of the branch predictors at reset on page B2-21.
B3.10.4 TLB lockdown
ARMv7 recognizes that any TLB lockdown scheme is heavily dependent on the microarchitecture, making
it inappropriate to define a common mechanism across all implementations. This means that:
ARMv7 does not require TLB lockdown support.
If TLB lockdown support is implemented, the lockdown mechanism is IMPLEMENTATION DEFINED.
However, key properties of the interaction of lockdown with the architecture must be documented as
part of the implementation documentation.
This means that:
In ARMv7, the TLB Type Register TLBTR does not define the lockdown scheme in use. This is a
change from previous versions of the architecture.
A region of the CP15 c10 encodings is reserved for IMPLEMENTATION DEFINED TLB functions, such
as TLB lockdown functions. The reserved encodings are those with:
— = {0, 1, 4, 8}
— all values of and .
See also The implementation defined TLB control operations on page B3-143.
An implementation might use some of the CP15 c10 encodings that are reserved for IMPLEMENTATION
DEFINED TLB functions to implement additional TLB control functions. These functions might include:
Unlock all locked TLB entries.
Preload into a specific level of TLB. This is beyond the scope of the PLI and PLD hint instructions.
B3.10.5 TLB maintenance
TLB maintenance operations provide a mechanism to invalidate entries from a TLB.
Any TLB operation might affect other TLB entries that are not locked down.
TLB maintenance operations are provided by CP15 c8 functions. The following operations are supported:
invalidate all unlocked entries in the TLB
invalidate a single TLB entry, by MVA, or MVA and ASID for a non-global entry
invalidate all TLB entries that match a specified ASID.
The Multiprocessing Extensions add the following operations:
invalidate all TLB entries that match a specified by MVA, regardless of the ASID
operations that apply across multiprocessors in the same Inner Shareable domain, see Multiprocessor
effects on TLB maintenance operations on page B3-62.
B3-56 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B