ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

c0, Memory Model Feature Register 3 (ID_MMFR3)
The CPUID Identification Scheme
The format of the ID_MMFR3 is:
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
Reserved,
RAZ
Supersection support, bits [31:28]
On a VMSA implementation, indicates whether Supersections are supported. Permitted
values are:
0b0000 Supersections supported.
0b1111 Supersections not supported.
All other values are reserved.
Note
The sense of this identification is reversed from the normal usage in the CPUID mechanism,
with the value of zero indicating that the feature is supported.
Bits [27:24] Reserved, RAZ.
Coherent walk, bits [23:20]
Indicates whether Translation table updates require a clean to the point of unification.
Permitted values are:
0b0000 Updates to the translation tables require a clean to the point of unification to
ensure visibility by subsequent translation table walks.
0b0001 Updates to the translation tables do not require a clean to the point of unification
to ensure visibility by subsequent translation table walks.
Bits [19:16] Reserved, RAZ.
Reserved,
RAZ
Coherent walk
Maintenance broadcast
BP maintain
Cache maintainence s/w
Cache maintainence MVA
Supersection support
Maintenance broadcast, bits [15:12]
Indicates whether Cache, TLB and branch predictor operations are broadcast. Permitted
values are:
0b0000 Cache, TLB and branch predictor operations only affect local structures.
0b0001 Cache and branch predictor operations affect structures according to
shareability and defined behavior of instructions. TLB operations only affect
local structures.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B5-17