ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Events
C3.4 Generation of debug events
The generation of Breakpoint and Watchpoint debug events can be dependent on the context of the
processor, including:
the current processor mode
the contents of the CONTEXTIDR
the Secure security state setting, if the processor implements Security Extensions.
The generation of debug events is also dependent on the state of the debug event generation logic:
Breakpoint debug events are dependent on the contents of the relevant Breakpoint Register Pair
(BRP)
Watchpoint debug events are dependent on the contents of the relevant Watchpoint Register Pair
(WRP)
Linked Breakpoint or Watchpoint debug events are dependent on the settings of a second BRP
Vector Catch debug events are dependent on the settings in the Vector Catch Register (DBGVCR)
OS Unlock Catch debug events are dependent on the setting of the Event Catch Register (DBGECR).
In addition, as shown in Table C3-1 on page C3-2, the generation of debug events is dependent on:
the invasive debug authentication settings, see Chapter C2 Invasive Debug Authentication
the values of the DBGDSCR.HDBGen and DBGDSCR.MDBGen bits, see Debug Status and Control
Register (DBGDSCR) on page C10-10.
The following events are guaranteed to take effect on the debug event generation logic by the end of the next
ISB operation, exception entry, or exception return:
Context changing operations, including:
— mode changes
— writes to the CONTEXTIDR
— security state changes.
Operations that change the state of the debug event generation logic, including:
— writes to BRP registers, for Breakpoint debug events, or Linked Breakpoint or Watchpoint
debug events
— writes to WRP registers, for Watchpoint debug events
— writes to the DBGVCR, for Vector Catch debug events
— writes to the DBGECR, for OS Unlock Catch debug events
— changes to the authentication signals
— writes to the DBGDSCR.
C3-40 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B