ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Application Level Memory Model
A3.1 Address space
The ARM architecture uses a single, flat address space of 2 32 8-bit bytes. Byte addresses are treated as
unsigned numbers, running from 0 to 2 32 - 1. The address space is also regarded as:
2 30 32-bit words:
— the address of each word is word-aligned, meaning that the address is divisible by 4 and the
last two bits of the address are 0b00
— the word at word-aligned address A consists of the four bytes with addresses A, A+1, A+2 and
A+3.
2 31 16-bit halfwords:
— the address of each halfword is halfword-aligned, meaning that the address is divisible by 2
and the last bit of the address is 0
— the halfword at halfword-aligned address A consists of the two bytes with addresses A and
A+1.
In some situations the ARM architecture supports accesses to halfwords and words that are not aligned to
the appropriate access size, see Alignment support on page A3-4.
Normally, address calculations are performed using ordinary integer instructions. This means that the
address wraps around if the calculation overflows or underflows the address space. Another way of
describing this is that any address calculation is reduced modulo 2 32 .
A3.1.1 Address incrementing and address space overflow
When a processor performs normal sequential execution of instructions, it effectively calculates:
(address_of_current_instruction) + (size_of_executed_instruction)
after each instruction to determine which instruction to execute next.
Note
The size of the executed instruction depends on the current instruction set, and might depend on the
instruction executed.
If this address calculation overflows the top of the address space, the result is UNPREDICTABLE. In other
words, a program must not rely on sequential execution of the instruction at address 0x00000000 after the
instruction at address:
0xFFFFFFFC, when a 4-byte instruction is executed
0xFFFFFFFE, when a 2-byte instruction is executed
0xFFFFFFFF, when a single byte instruction is executed.
A3-2 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B