ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
The format of the PMOVSR is:
31 30 N N-1 0
C RAZ/WI Event counter overflow flags, Px, for x = 0 to (N-1)
Note
In the description of the PMOVSR, N and x have the meanings used in the description of the
PMCNTENSET Register, see c9, Count Enable Set Register (PMCNTENSET) on page C10-108.
C, bit [31] PMCCNTR overflow flag.
Table C10-27 shows the behavior of this bit on reads and writes.
Bits [30:N] RAZ/WI.
Px, bit [x], for x = 0 to (N-1)
Event counter x, PMNx, overflow flag.
Table C10-27 shows the behavior of this bit on reads and writes.
The contents of the PMOVSR are UNKNOWN on a core logic reset.
Table C10-27 Read and write bit values for the PMOVSR
Value Meaning on read Action on write
0 Counter has not overflowed No action, write is ignored
1 Counter has overflowed Clear flag to 0
Note
The overflow flag values for individual counters are retained until cleared to 0 by a write to the PMOVSR
or processor reset, even if the counter is later disabled by writing to the PMCNTENCLR register or through
the PMCR.E Enable bit. The overflow flags are also not cleared to 0 when the counters are reset through the
Event counter reset or Clock counter reset bits in the PMCR.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C10-111