ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
In v6 Debug and v6.1 Debug, register 196 is not defined.
The format of the DBGPRCR is:
31
Bits [31:3] Reserved, UNK/SBZP.
Hold non-debug logic reset, bit [2]
Reserved, UNK/SBZP
Hold non-debug logic reset
Warm reset request
DBGnoPWRDWN
The effects of the possible values of this bit are:
0 Do not hold the non-debug logic reset on power-up or warm reset.
1 Hold the non-debug logic of the processor in reset on power-up or warm reset.
The processor is held in this state until this flag is cleared to 0.
Hold non-debug logic reset is an IMPLEMENTATION DEFINED feature. If it is implemented
writing 1 to this bit means the non-debug logic of the processor is held in reset after a
power-up or warm reset.
Note
This bit never affects system power-up, because when implemented it resets to 0.
An external debugger can use this bit to prevent the processor running again before the
debugger has had the chance to detect a power-down occurrence and restore the state of the
debug registers inside the core power domain. Also, this bit can be used in conjunction with
an external reset controller to take the processor into reset and hold it there while the rest of
the system comes out of reset. This means a debugger can hold the processor in reset while
programming other debug registers.
The effect of this bit depends on the state of the external debug interface signals:
If the processor implements the Security Extensions, the value of this bit is ignored
unless both the external debug interface signals DBGEN and SPIDEN are HIGH,
meaning that invasive debug is permitted in all processor states and modes.
If the processor does not implement the Security Extensions, the value of this bit is
ignored unless DBGEN is HIGH.
For details of invasive debug authentication see Chapter C2 Invasive Debug Authentication.
If both features are supported, the bit can be written at the same time as the Warm reset
request bit to force the processor into reset and hold it there, for example while
programming other debug registers such as setting the Halt request bit of the DBGDRCR to
take the processor into Debug state on leaving Reset. For more information, see Debug Run
Control Register (DBGDRCR), v7 Debug only on page C10-29.
C10-32 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B
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