ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

B4.2 Memory access control
Protected Memory System Architecture (PMSA)
Access to a memory region is controlled by the access permission bits for each region, held in the DRACR
and IRACR. For descriptions of the registers see:
c6, Data Region Access Control Register (DRACR) on page B4-64
c6, Instruction Region Access Control Register (IRACR) on page B4-65.
B4.2.1 Access permissions
Access permission bits control access to the corresponding memory region. If an access is made to an area
of memory without the required permissions, a Permission fault is generated. In the appropriate Region
Access Control Register:
the AP bits determine the access permissions
the XN bit provides an additional permission bit for instruction fetches.
The access permissions are a three-bit field, DRACR.AP[2:0] or IRACR.AP[2:0]. Table B4-3 shows the
possible values of this field.
AP[2:0]
Privileged
permissions
User
permissions
Description
Table B4-3 Access permissions
000 No access No access All accesses generate a Permission fault
001 Read/Write No access All User mode accesses generate Permission faults
010 Read/Write Read-only User mode write accesses generate Permission faults
011 Read/Write Read/Write Full access
100 UNPREDICTABLE UNPREDICTABLE Reserved
101 Read-only No Access Privileged read-only, all other accesses generate
Permission faults
110 Read-only Read-only All write accesses generate Permission faults.
111 UNPREDICTABLE UNPREDICTABLE Reserved
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B4-9