ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Protected Memory System Architecture (PMSA)
NMFI, bit [27]
Bit [26] RAZ/SBZP.
Non-Maskable Fast Interrupts enable:
0 Fast interrupts (FIQs) can be masked in the CPSR
1 Fast interrupts are non-maskable.
This bit is read-only. It is IMPLEMENTATION DEFINED whether an implementation supports
Non-Maskable Fast Interrupts (NMFIs):
If NMFIs are not supported then this bit is RAZ/WI.
If NMFIs are supported then this bit is determined a configuration input signal.
For more information, see Non-maskable fast interrupts on page B1-18.
EE, bit [25] Exception Endianness bit. The value of this bit defines the value of the CPSR.E bit on entry
to an exception vector, including reset. The permitted values of this bit are:
0 Little endian
1 Big endian.
This is a read/write bit. An implementation can include a configuration input signal that
determines the reset value of the EE bit. If the implementation does not include a
configuration signal for this purpose then this bit resets to zero.
If IE == 1 and EE == 0, behavior is UNPREDICTABLE.
VE, bit [24] Interrupt Vectors Enable bit. This bit controls the vectors used for the FIQ and IRQ
interrupts. The permitted values of this bit are:
0 Use the FIQ and IRQ vectors from the vector table, see the V bit entry
1 Use the IMPLEMENTATION DEFINED values for the FIQ and IRQ vectors.
For more information, see Vectored interrupt support on page B1-32.
If the implementation does not support IMPLEMENTATION DEFINED FIQ and IRQ vectors
then this bit is RAZ/WI.
Bit [23] RAO/SBOP.
U, bit [22] In ARMv7 this bit is RAO/SBOP, indicating use of the alignment model described in
Alignment support on page A3-4.
For details of this bit in earlier versions of the architecture see Alignment on page AppxG-6.
FI, bit [21] Fast Interrupts configuration enable bit. This bit can be used to reduce interrupt latency in
an implementation by disabling IMPLEMENTATION DEFINED performance features. The
permitted values of this bit are:
0 All performance features enabled.
1 Low interrupt latency configuration. Some performance features disabled.
If the implementation does not support a mechanism for selecting a low interrupt latency
configuration this bit is RAZ/WI.
For more information, see Low interrupt latency configuration on page B1-43.
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