ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

nSUHD_imp, bit [14]
Debug Registers Reference
1 DBGDEVID is implemented, see Debug Device ID Register (DBGDEVID) on
page C10-6.
This bit is always RAZ in ARMv6.
Secure User halting debug not implemented bit. When the Security Extensions are
implemented, the meanings of the values of this bit are:
0 Secure User halting debug is implemented
1 Secure User halting debug is not implemented.
If the Security Extensions are not implemented:
Secure User halting debug cannot be implemented
this bit is RAZ.
A v6.1 Debug processor that implements the Security Extensions must support Secure User
halting debug. In v6.1 Debug this bit is always RAZ.
See also Chapter C2 Invasive Debug Authentication.
PCSR_imp, bit [13]
Program Counter Sampling Register (DBGPCSR) implemented as register 33 bit. The
meanings of the values of this bit are:
0 DBGPCSR is not implemented as register 33
1 DBGPCSR is implemented as register 33.
Note
In v7 Debug, the DBGPCSR can be implemented as register 33, as register 40, or as both
register 33 and register 40, as described in Implemented Program Counter sampling
registers on page C8-2. The PCSR_imp bit only indicates whether it is implemented as
register 33. For details of how to determine whether it is implemented as register 40 see
Debug Device ID Register (DBGDEVID) on page C10-6.
In ARMv6, the Program Counter Sampling Register is an IMPLEMENTATION DEFINED
feature of the external debug interface and is not indicated in the DBGDIDR. This bit is
always RAZ in ARMv6.
See also Program Counter Sampling Register (DBGPCSR) on page C10-38.
SE_imp, bit [12]
Security Extensions implemented bit. The meanings of the values of this bit are:
0 Security Extensions are not implemented
1 Security Extensions are implemented.
v6 Debug is not a permitted option for an implementation that includes the Security
Extensions. This bit is RAZ on a v6 Debug implementation.
Bits [11:8] Reserved, RAZ.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C10-5