ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Protected Memory System Architecture (PMSA)
LoUIS, bits [23:21]
Level of Unification Inner Shareable for the cache hierarchy, see Clean, Invalidate, and
Clean and Invalidate on page B2-11. This field is RAZ in implementations that do not
implement the Multiprocessing extension.
CtypeX, bits [3(x - 1) + 2:3(x - 1)], for x = 1 to 7
Cache type fields. Indicate the type of cache implemented at each level, from Level 1 up to
a maximum of seven levels of cache hierarchy. The Level 1 cache type field, Ctype1, is bits
[2:0], see register diagram. Table B4-15 shows the possible values for each CtypeX field.
If you read the Cache type fields from Ctype1 upwards, once you have seen a value of
0b000, no caches exist at further out levels of the hierarchy. So, for example, if Ctype3 is
the first Cache type field with a value of 0b000, the values of Ctype4 to Ctype7 must be
ignored.
The CLIDR describes only the caches that are under the control of the processor.
Accessing the CLIDR
To access the CLIDR you read the CP15 registers with set to 1, set to c0, set to c0, and
set to 1. For example:
MRC p15,1,,c0,c0,1 ; Read CP15 Cache Level ID Register
Table B4-15 Ctype bit values
CtypeX bits Meaning, cache implemented at this level
000 No cache
001 Instruction cache only
010 Data cache only
011 Separate instruction and data caches
100 Unified cache
101, 11X Reserved
B4-42 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B