ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.59 LDR (literal)
Load Register (literal) calculates an address from the PC value and an immediate offset, loads a word from
memory, and writes it to a register. For information about memory accesses see Memory accesses on
page A8-13.
Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
LDR ,
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 0 1 Rt imm8
t = UInt(Rt); imm32 = ZeroExtend(imm8:’00’, 32); add = TRUE;
Encoding T2
LDR.W ,
ARMv6T2, ARMv7
LDR.W ,[PC,#-0] Special case
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 0 U 1 0 1 1 1 1 1 Rt imm12
t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == ‘1’);
if t == 15 && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
Encoding A1
LDR ,
ARMv4*, ARMv5T*, ARMv6*, ARMv7
LDR ,[PC,#-0] Special case
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 0 1 0 (1) U 0 (0) 1 1 1 1 1 Rt imm12
t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == ‘1’);
Assembler syntax
LDR , Normal form
LDR , [PC, #+/-] Alternative form
where:
See Standard assembler syntax fields on page A8-7.
The destination register. The SP can be used. The PC can be used, provided the instruction
is either outside an IT block or the last instruction of an IT block. If the PC is used, the
instruction branches to the address (data) loaded to the PC. In ARMv5T and above, this
branch is an interworking branch, see Pseudocode details of operations on ARM core
registers on page A2-12.
A8-122 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B