ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
VDIV.F64 {,} , Encoded as sz = 1
VDIV.F32 {,} , Encoded as sz = 0
where:
See Standard assembler syntax fields on page A8-7.
Instruction Details
, , The destination register and the operand registers, for a double-precision operation.
, , The destination register and the operand registers, for a single-precision operation.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckVFPEnabled(TRUE);
if dp_operation then
D[d] = FPDiv(D[n], D[m], TRUE);
else
S[d] = FPDiv(S[n], S[m], TRUE);
Exceptions
Undefined Instruction.
Floating-point exceptions: Invalid Operation, Division by Zero, Overflow, Underflow, Inexact, Input
Denormal.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-591