ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Level 2 cache support
ARMv4 and ARMv5 Differences
The recommended method for adding closely coupled level 2 cache support from ARMv5TE is to define
equivalent operations to the level 1 support with == 1 in the appropriate MCR instructions. The
operations in Table H-21 on page AppxH-49 that are supported are IMPLEMENTATION DEFINED.
H.7.9 c7, Miscellaneous functions
The Wait For Interrupt operation is used in some implementations as part of a power management support
scheme. The operation is deprecated in ARMv6 and not supported in ARMv7 (it behaves as a NOP
instruction).
Barrier operations are used for system correctness to ensure visibility of memory accesses to other agents
in a system. For ARMv4 and ARMv5 the requirement for and use of barrier operations is IMPLEMENTATION
DEFINED. Barrier functionality is formally defined as part of the memory architecture enhancements
introduced in ARMv6.
Table H-22 summarizes the MCR instruction encoding details.
H.7.10 c8, VMSA TLB support
Table H-22 Memory barrier register support
Operation CRn opc1 CRm opc2
Wait For Interrupt (CP15WFI) c7 0 c0 4
Instruction Synchronization Barrier (CP15ISB) a
Data Synchronization Barrier (CP15DSB) b
c7 0 c5 4
c7 0 c10 4
Data Memory Barrier (CP15DMB) c7 0 c10 5
a. This operation was previously known as Prefetch Flush (PF or PFF).
b. This operation was previously known as Data Write Barrier or Drain Write Buffer (DWB).
Table H-23 illustrates TLB operation provision in ARMv4 and ARMv5. All TLB operations are performed
as MCR instructions and are a subset of the operations available in ARMv7. See CP15 c8, TLB maintenance
operations on page B3-138.
Table H-23 TLB operation support
Operation CRn opc1 CRm opc2
Invalidate Instruction TLB c8 0 c5 0
Invalidate Instruction TLB Entry (by MVA) c8 0 c5 1
Invalidate Data TLB c8 0 c6 0
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. AppxH-51