ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug event generation conditions defined by the DBGBCR
Debug Events
For each BRP, the DBGBCR defines some conditions for generating a Breakpoint debug event, using the
following register fields:
Breakpoint enable
Controls whether this BRP is enabled.
Privileged mode control
Controls whether this BRP defines a Breakpoint debug event that can occur:
only in User mode
only in a privileged mode
only in User, System or Supervisor modes
in any mode.
Security state control
If the processor implements the Security Extensions, this field controls whether this BRP
defines a Breakpoint debug event that can occur only in Secure state, only in Non-secure
state, or in either security state.
For more information, including the differences in different versions of the Debug architecture, see
Breakpoint Control Registers (DBGBCR) on page C10-49.
When two BRPs are linked to define a single Breakpoint debug event, the BRP that defines the IVA
comparison also defines the privileged mode control and security state control, see Additional conditions
for linked BRPs on page C3-15 for more information.
Other information in the DBGBCR
In addition to defining these conditions for generating a Breakpoint debug event, the DBGBCR controls the
following:
The DBGBVR meaning field defines the breakpoint type. The following sections describe all of the
breakpoint types:
— IVA comparisons for Debug event generation on page C3-8
— Context ID comparisons for Debug event generation on page C3-13.
The Linked BRP number field specifies whether the BRP is linked to another BRP. If this BRP is
linked, this field gives the number of the linked BRP. For more information see Additional conditions
for linked BRPs on page C3-15.
For an IVA comparison, the DBGBVR defines a word-aligned address, and the Byte address select
field specifies the bytes in that word that comprise the breakpointed instruction, see IVA comparisons
for Debug event generation on page C3-8.
For an IVA comparison in v7 Debug, the Address range mask field optionally specifies a bitmask that
defines the low-order bits of the IVA and DBGBVR values that are excluded from the comparison,
see IVA comparisons for Debug event generation on page C3-8.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C3-7