ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
Z, bit [11] Branch prediction enable bit. This bit is used to enable branch prediction, also called
program flow prediction:
0 Program flow prediction disabled
1 Program flow prediction enabled.
When the Security Extensions are implemented, this bit is banked between the Secure and
Non-secure versions of the register.
If program flow prediction cannot be disabled, this bit is RAO/WI. Program flow prediction
includes all possible forms of speculative change of instruction stream prediction. Examples
include static prediction, dynamic prediction, and return stacks.
If the implementation does not support program flow prediction this bit is RAZ/WI.
SW, bit[10] SWP/SWPB Enable bit. This bit enables the use of SWP and SWPB instructions:
0 SWP and SWPB are UNDEFINED
1 SWP and SWPB perform as described in SWP, SWPB on page A8-432.
When the Security Extensions are implemented, this bit is banked between the Secure and
Non-secure versions of the register. The bit is reset to 0.
This is part of the Multiprocessing Extensions. In implementations that do not implement
the Multiprocessing Extensions this bit is RAZ and SWP and SWPB instructions perform as
described in SWP, SWPB on page A8-432.
Note
Bits [9:8] RAZ/SBZP.
At reset, this bit disables SWP and SWPB. This means that operating systems have to choose to
use SWP or SWPB.
B, bit [7] In ARMv7 this bit is RAZ/SBZP, indicating use of the endianness model described in
Endian support on page A3-7.
For details of this bit in earlier versions of the architecture see Endian support on
page AppxG-7 and Endian support on page AppxH-7.
Bits [6:3] RAO/SBOP.
C, bit [2] Cache enable bit: This is a global enable bit for data and unified caches:
0 Data and unified caches disabled
1 Data and unified caches enabled.
When the Security Extensions are implemented, this bit is banked between the Secure and
Non-secure versions of the register.
If the system does not implement any data or unified caches that can be accessed by the
processor, at any level of the memory hierarchy, this bit is RAZ/WI.
If the system implements any data or unified caches that can be accessed by the processor
then it must be possible to disable them by setting this bit to 0.
Cache enabling and disabling on page B2-8 describes the effect of enabling the caches.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B3-101