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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Instruction Details<br />

A8.6.284 VCGT (register)<br />

VCGT (Vector Compare Greater Than) takes each element in a vector, <strong>and</strong> compares it with the corresponding<br />

element of a second vector. If the first is greater than the second, the corresponding element in the<br />

destination vector is set to all ones. Otherwise, it is set to all zeros.<br />

The oper<strong>and</strong> vector elements can be any one of:<br />

8-bit, 16-bit, or 32-bit signed integers<br />

8-bit, 16-bit, or 32-bit unsigned integers<br />

32-bit floating-point numbers.<br />

The result vector elements are bitfields the same size as the oper<strong>and</strong> vector elements.<br />

Encoding T1 / A1 Advanced SIMD<br />

VCGT. , , an integer type<br />

VCGT. , , an integer type<br />

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

1 1 1 U 1 1 1 1 0 D size Vn Vd 0 0 1 1 N Q M 0 Vm<br />

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

1 1 1 1 0 0 1 U 0 D size Vn Vd 0 0 1 1 N Q M 0 Vm<br />

if Q == ‘1’ && (Vd == ‘1’ || Vn == ‘1’ || Vm == ‘1’) then UNDEFINED;<br />

if size == ‘11’ then UNDEFINED;<br />

type = if U == ‘1’ then VCGTtype_unsigned else VCGTtype_signed;<br />

esize = 8

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