ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.189 STM / STMIA / STMEA
Store Multiple Increment After (Store Multiple Empty Ascending) stores multiple registers to consecutive
memory locations using an address from a base register. The consecutive memory locations start at this
address, and the address just above the last of those locations can optionally be written back to the base
register.
For details of related system instructions see STM (user registers) on page B6-22.
Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7 (not in ThumbEE)
STM !,
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 0 Rn register_list
n = UInt(Rn); registers = ‘00000000’:register_list; wback = TRUE;
if BitCount(registers) < 1 then UNPREDICTABLE;
Encoding T2 ARMv6T2, ARMv7
STM.W {!},
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 0 0 0 1 0 W 0 Rn (0) M (0) register_list
n = UInt(Rn); registers = ‘0’:M:’0’:register_list; wback = (W == ‘1’);
if n == 15 || BitCount(registers) < 2 then UNPREDICTABLE;
if wback && registers == ‘1’ then UNPREDICTABLE;
Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
STM {!},
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 1 0 0 0 1 0 W 0 Rn register_list
n = UInt(Rn); registers = register_list; wback = (W == ‘1’);
if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
Assembler syntax
STM {!},
where:
See Standard assembler syntax fields on page A8-7.
The base register. The SP can be used.
! Causes the instruction to write a modified value back to . Encoded as W = 1.
If ! is omitted, the instruction does not change in this way. Encoded as W = 0.
A8-374 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B