ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Register Interfaces
C6.6 The CP14 debug register interfaces
This section contains the following subsections:
The Baseline CP14 debug register interface
Extended CP14 interface on page C6-33
CP14 debug registers access permissions on page C6-36.
C6.6.1 The Baseline CP14 debug register interface
Table C6-4 lists the set of CP14 debug instructions for accessing the debug registers that must be
implemented.
All MRC and MCR instructions with = 0b1110 and = 0b000 are debug instructions:
Some of these instructions are defined in Table C6-4.
Additional instructions are defined in Extended CP14 interface on page C6-33
All other instructions are reserved for use by the Debug architecture. The behavior of reserved
instructions is defined in CP14 debug registers access permissions on page C6-36.
All MRC and MCR instructions with = 0b1110 and = 0b001 are used by the trace extension.
Other values of are not used by the Debug architecture.
All LDC and STC instructions with = 0b1110 that are not listed below are reserved for use by the
Debug architecture and are currently UNDEFINED. All CDP, MRC2, MCR2, LDC2, STC2, LDCL, STCL, LDC2L, and STC2L
instructions with = 0b1110 are UNDEFINED.
Instructions that access registers that are only available in v7 Debug are UNDEFINED in earlier versions of
the Debug architecture. For example, the read from DBGDRAR performed by MRC p14,0,,c1,c0,0 is
UNDEFINED in v6 Debug and v6.1 Debug, but is permitted in v7 Debug.
refers to any of the general-purpose registers R0-R14. Use of APSR_nzcv is UNPREDICTABLE except
where stated. Use of R13 is UNPREDICTABLE in Thumb and ThumbEE state, and is deprecated in ARM state.
Table C6-4 Baseline CP14 debug instructions
Instruction Mnemonic Version Name and reference to description
MRC p14,0,,c0,c0,0 DBGDIDR All Debug ID Register (DBGDIDR) on page C10-3
MRC p14,0,,c1,c0,0 DBGDRAR v7 only Debug ROM Address Register (DBGDRAR) on
page C10-7
MRC p14,0,,c2,c0,0 DBGDSAR v7 only Debug Self Address Offset Register (DBGDSAR)
on page C10-8
C6-32 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B