ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

C10.3.3 Debug Run Control Register (DBGDRCR), v7 Debug only
Debug Registers Reference
The Debug Run Control Register, DBGDRCR, requests the processor to enter or leave Debug state. It is also
used to clear to 0 the sticky exception bits in the DBGDSCR.
The DBGDRCR is:
debug register 36, at offset 0x090
a write-only register
implemented only in v7 Debug
when the Security Extensions are implemented, a Common register.
In v6 Debug and v6.1 Debug, register 36 is not defined.
The format of the DBGDRCR is:
31 5 4 3 2 1 0
Bits [31:5] Reserved, SBZ.
Cancel BIU Requests, bit [4]
Reserved, SBZ
Cancel BIU Requests
Clear Sticky Pipeline Advance flag
Clear Sticky Exceptions flags
Restart request
Halt request
Cancel Bus Interface Unit Requests bit. The actions on writing to this bit are:
0 no action
1 cancel pending accesses.
See Cancel Bus Interface Unit (BIU) Requests on page C10-30. It is IMPLEMENTATION
DEFINED whether this feature is supported. If this feature is not implemented, writes to this
bit are ignored.
It is UNPREDICTABLE whether a write of 1 to this bit has any effect when the processor is
powered-down.
Clear Sticky Pipeline Advance flag, bit [3]
This bit is used to clear the DBGDSCR.PipeAdv bit, the Sticky Pipeline Advance bit, to 0.
The actions on writing to this bit are:
0 no action
1 clear the DBGDSCR.PipeAdv bit to 0.
When the processor is powered down, it is UNPREDICTABLE whether a write of 1 to this bit
clears DBGDSCR.PipeAdv to 0.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C10-29