ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

A3.3 Endian support
The rules in Address space on page A3-2 require that for a word-aligned address A:
the word at address A consists of the bytes at addresses A, A+1, A+2 and A+3
the halfword at address A consists of the bytes at addresses A and A+1
the halfword at address A+2 consists of the bytes at addresses A+2 and A+3.
the word at address A therefore consists of the halfwords at addresses A and A+2.
Application Level Memory Model
However, this does not specify completely the mappings between words, halfwords, and bytes.
A memory system uses one of the two following mapping schemes. This choice is known as the endianness
of the memory system.
In a little-endian memory system:
the byte or halfword at a word-aligned address is the least significant byte or halfword in the word at
that address
the byte at a halfword-aligned address is the least significant byte in the halfword at that address.
In a big-endian memory system:
the byte or halfword at a word-aligned address is the most significant byte or halfword in the word at
that address
the byte at a halfword-aligned address is the most significant byte in the halfword at that address.
For a word-aligned address A, Table A3-3 and Table A3-4 on page A3-8 show the relationship between:
the word at address A
the halfwords at addresses A and A+2
the bytes at addresses A, A+1, A+2 and A+3.
Table A3-3 shows this relationship for a big-endian memory system, and Table A3-4 on page A3-8 shows
the relationship for a little-endian memory system.
Table A3-3 Big-endian memory system
MSByte MSByte - 1 LSByte + 1 LSByte
Word at Address A
Halfword at Address A Halfword at Address A+2
Byte at Address A Byte at Address A+1 Byte at Address A+2 Byte at Address A+3
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