ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Note
It is important to distinguish between:
The System Level Programmers’ Model
Figure B1-2 Security state, Monitor mode, and the SCR.NS bit
Monitor mode This is a processor mode that is only available when the Security Extensions are
implemented. It is used in normal operation, as a mechanism to transfer between Secure and
Non-secure state, as described in this section.
Monitor debug-mode
CP15SCR.NS = 1
(Non-secure)
SMC
Supervisor
FIQ
IRQ
Undef
Abort
System
Non-secure
privileged modes
Non-secure
state
Monitor
This is a debug mode and is available regardless of whether the Security Extensions are
implemented. For more information, see About the ARM Debug architecture on page C1-3.
Changing from Secure to Non-secure state
The security state is controlled by the SCR.NS bit, and ARM recommends that the SCR is modified only in
Monitor mode. Monitor mode is responsible for switching between Secure and Non-secure states.
To return to Non-secure state, set the SCR.NS bit to 1 and then perform an exception return.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B1-27
MCR
CP15SCR.NS = 0
(Secure)
Supervisor
FIQ
IRQ
Undef
Abort
System
User User
Secure
state
SMC ‡
Secure privileged
modes other than
Monitor mode
‡ or other mode
changing method