ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
0b101 Linked Instruction Virtual Address mismatch
Compare:
the byte address select bits, bits [8:5], and the associated
DBGBVR[31:2], against the IVA of the instruction
the security state control and privileged mode control bits,
bits [15:14,2:1], against the state of the processor.
This BRP is linked with the BRP indicated by DBGBCR[19:16]. Generate a
Breakpoint debug event on a joint IVA mismatch (IVA not equal), state match
and Context ID match. For more information, see Linked comparisons on
page C10-59.
Note
Linked IVA mismatch is not supported in v6 Debug.
See Unpredictable behavior on Software debug events on page C3-24 for
additional restrictions for this type of breakpoint when using Monitor
debug-mode.
0b11x Reserved
Generation of Breakpoint debug events is UNPREDICTABLE.
Summary of breakpoint generation options on page C10-58 shows what comparisons are
made for each permitted value of this field.
Linked BRP number, bits [19:16]
If this BRP is programmed for Linked IVA match or mismatch then this field must be
programmed with the number of the BRP that holds the Context ID to be used for the
combined IVA and Context ID comparison, otherwise, this field must be programmed to
0b0000.
If this field is programmed with a value other than zero or the number of a BRP that supports
Context ID comparison then reading this register returns an UNKNOWN value for this field.
The generation of Breakpoint debug events is UNPREDICTABLE if either:
this BRP is not programmed for Linked IVA match or mismatch and this field is not
programmed to 0b0000
this BRP is programmed for Linked IVA match or mismatch and the BRP indicated
by this field does not support Context ID comparison or is not programmed for
Linked Context ID match.
See also Generation of debug events on page C3-40.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C10-53