ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
LDR , [ {, #+/-}] Offset: index==TRUE, wback==FALSE
LDR , [, #+/-]! Pre-indexed: index==TRUE, wback==TRUE
LDR , [], #+/- Post-indexed: index==FALSE, wback==TRUE
where:
See Standard assembler syntax fields on page A8-7.
Instruction Details
The destination register. The SP can be used. The PC can be used, provided the instruction
is either outside an IT block or the last instruction of an IT block. If the PC is used, the
instruction branches to the address (data) loaded to the PC. In ARMv5T and above, this
branch is an interworking branch, see Pseudocode details of operations on ARM core
registers on page A2-12.
The base register. The SP can be used. For PC use see LDR (literal) on page A8-122.
+/- Is + or omitted if the immediate offset is to be added to the base register value (add == TRUE),
or – if it is to be subtracted (add == FALSE). #0 and #-0 generate different instructions.
The immediate offset used to form the address. For the offset addressing syntax, can
be omitted, meaning an offset of 0. Values are:
Encoding T1 multiples of 4 in the range 0-124
Encoding T2 multiples of 4 in the range 0-1020
Encoding T3 any value in the range 0-4095
Encoding T4 any value in the range 0-255.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); NullCheckIfThumbEE(n);
offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
address = if index then offset_addr else R[n];
data = MemU[address,4];
if wback then R[n] = offset_addr;
if t == 15 then
if address == ‘00’ then LoadWritePC(data); else UNPREDICTABLE;
elsif UnalignedSupport() || address = ‘00’ then
R[t] = data;
else R[t] = bits(32) UNKNOWN; // Can only apply before ARMv7
Exceptions
Data Abort.
ThumbEE instruction
ThumbEE has additional LDR (immediate) encodings. For details see LDR (immediate) on page A9-19.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-119