ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Note
The CPUID Identification Scheme
in the SIMD_instrs field, the value of 0b0010 is reserved
the SXTAB16, SXTB16, UXTAB16, and UXTB16 instructions are available only if both:
— the Extend_instrs attribute is 0b0010 or greater
— the SIMD_instrs attribute is 0b0011 or greater.
Saturate_instrs, bits [3:0]
Indicates the supported Saturate instructions. Permitted values are:
0b0000 None supported. This means no non-Advanced SIMD saturate instructions are
supported.
0b0001 Adds support for the QADD, QDADD, QDSUB, and QSUB instructions, and for the Q bit
in the PSRs.
c0, Instruction Set Attribute Register 4 (ID_ISAR4)
The format of the ID_ISAR4 is:
31 28 27 24 23 20 19
16 15 12 11 8 7 4 3 0
SWP_frac
PSR_M
_instrs
SWP_frac, bits [31:28]
SynchPrim
_instrs_frac
Barrier
_instrs
SMC
_instrs
Writeback
_instrs
WithShifts
_instrs
Unpriv
_instrs
Indicates support for the memory system locking the bus for SWP or SWPB instructions.
Permitted values are:
0b0000 SWP or SWPB not supported.
0b0001 SWP or SWPB supported but only in a uniprocessor context. SWP and SWPB do not
guarantee whether memory accesses from other masters can come between the
load memory access and the store memory access of the SWP or SWPB.
This field is valid only if the Swap_instrs field in ID_ISAR0 is zero.
PSR_M_instrs, bits [27:24]
Indicates the supported M profile instructions to modify the PSRs. Permitted values are:
0b0000 None supported.
0b0001 Adds support for the M profile forms of the CPS, MRS and MSR instructions.
SynchPrim_instrs_frac, bits [23:20]
This field is used with the SynchPrim_instrs field of ID_ISAR3 to indicate the supported
Synchronization Primitive instructions. Table B5-2 on page B5-30 shows the permitted
values of these fields.
All combinations of SynchPrim_instrs and SynchPrim_instrs_frac not shown in Table B5-2
on page B5-30 are reserved.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B5-31