ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

C1.4 Register interfaces
Introduction to the ARM Debug Architecture
This section gives a brief description of the different debug register interfaces defined by v7 Debug. The
most important distinction is between:
the external debug interface, that defines how an external debugger can access the v7 Debug
resources
the processor interface, that describes how an ARMv7 processor can access its own debug resources.
For v7 Debug, ARM recommends an external debug interface based on the ARM Debug Interface v5
Architecture Specification (ADIv5). The most significant difference between ADIv5 and the interface
recommended by v6 Debug and v6.1 Debug is that ADIv5 supports debug over power-down of the
processor.
Although the ADIv5 interface is not required for compliance with ARMv7, the ARM RealView ® tools
require this interface to be implemented.
ADIv5 supports both a JTAG wire interface and a low pin-count Serial Wire (SW) interface. The RealView
tools support either wire interface.
An ADIv5 interface enables a debug object, such as an ARMv7 processor, to abstract a set of resources as
a memory-mapped peripheral. Accesses to debug resources are made as 32-bit read/write transfers.
Power-down debug is supported by introducing the abstraction that accesses to certain resources can return
an error response when they are unavailable, just as a memory-mapped peripheral can return a
slave-generated error response in exceptional circumstances.
v7 Debug requires software executing on the processor to be able to access all debug registers. To provide
access to a particular basic subset of debug registers, v7 Debug requires implementation of the Baseline
Coprocessor 14 (CP14) Interface, see The Baseline CP14 debug register interface on page C6-32. To
provide access to the rest of the debug registers v7 Debug permits one of two options:
An Extended CP14 interface. This is similar to the requirement of v6 Debug and v6.1 Debug.
A memory-mapped interface.
An implementation can include both of these options.
ARMv7 does not permit all combinations of debug, trace, and performance monitor register interfaces.
There are three options for ARMv7 implementations, shown in Table C1-2 on page C1-10. In a number of
cases an optional memory-mapped interface is permitted, indicated by brackets. ARM recommends that if
the optional memory-mapped interface is implemented for either the debug interface or the trace interface
then it is implemented for both of these interfaces.
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