ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

C5.4 Executing instructions in Debug state
Debug State
In Debug state the processor executes instructions issued through the Instruction Transfer Register, see
Instruction Transfer Register (DBGITR) on page C10-46. This mechanism is enabled through
DBGDSCR[13], see Debug Status and Control Register (DBGDSCR) on page C10-10.
The following rules and restrictions apply to instructions that can be executed in this manner in Debug state:
The processor instruction set state always corresponds to the state indicated by the CPSR.J and
CPSR.T execution state bits. However, the processor always interprets the instructions issued through
the DBGITR as ARM instruction set opcodes, regardless of the setting of the CPSR.J and CPSR.T
execution state bits.
Some ARM instructions are UNPREDICTABLE if executed in Debug state. These instructions are
either:
— identified as UNPREDICTABLE in this list
— shown as UNPREDICTABLE in Table C5-2 on page C5-10.
Otherwise, except for the value read from the PC, instructions executed in Debug state operate as
specified for ARM state. Behavior of the PC and CPSR in Debug state on page C5-7 specifies the
value read from the PC.
The CPSR.IT execution state bits are ignored. This means that instructions issued through the
DBGITR do not fail their condition tests unexpectedly. However, the condition code field in an ARM
instruction is honored.
The CPSR.IT execution state bits are preserved and do not change when instructions are executed,
unless an instruction that modifies those bits explicitly is executed.
The branch instructions B, BL, BLX (immediate), and BLX (register) are UNPREDICTABLE in Debug state.
The hint instructions WFI, WFE and YIELD are UNPREDICTABLE in Debug state.
All memory read and memory write instructions with the PC as the base address register read an
UNKNOWN value for the base address.
Certain instructions that normally update the CPSR can be UNPREDICTABLE in Debug state, see
Writing to the CPSR in Debug state on page C5-10.
Instructions that load a value from memory into the PC are UNPREDICTABLE in Debug state.
Conditional instructions that write explicitly to the PC are UNPREDICTABLE in Debug state.
There are additional restrictions on data-processing instructions that write to the PC. See
Data-processing instructions with the PC as the target in Debug state on page C5-12.
The exception-generating instructions SVC, SMC and BKPT are UNPREDICTABLE in Debug state.
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