ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Invalidate TLB entries by MVA all ASID
Virtual Memory System Architecture (VMSA)
The Invalidate TLB entries by MVA all ASID operations invalidate all TLB entries that matches the MVA
provided as an argument to the operation regardless of the ASID. The register format required is:
31 12 11 0
MVA SBZ
Accessing the CP15 c8 TLB maintenance operations
To perform one of the TLB maintenance operations you write the CP15 registers with == 0,
==c8, and and set to the values shown in Table B3-35 on page B3-139. That is:
MCR p15,0,,c8,,
For example:
MCR p15,0,,c8,c5,0 ; Invalidate all unlocked entries in Instruction TLB
MCR p15,0,,c8,c6,2 ; Invalidate Data TLB entries on ASID match
B3.12.35 CP15 c9, Cache and TCM lockdown registers and performance monitors
Some CP15 c9 encodings are reserved for IMPLEMENTATION DEFINED memory system functions, in
particular:
cache control, including lockdown
TCM control, including lockdown
branch predictor control.
Additional CP15 c9 encodings are reserved for performance monitors. These encodings fall into two groups:
the optional performance monitors, described in Chapter C9 Performance Monitors
additional IMPLEMENTATION DEFINED performance monitors.
The reserved encodings permit implementations that are compatible with previous versions of the ARM
architecture, in particular with the ARMv6 requirements. Figure B3-21 shows the permitted CP15 c9
register encodings.
CRn opc1 CRm opc2
c9 {0-7} {c0-c2} {0-7} ‡ Reserved for Branch Predictor, Cache and TCM operations
{c5-c8} {0-7} ‡ Reserved for Branch Predictor, Cache and TCM operations
{c12-c14} {0-7} Reserved for ARM-recommended Performance Monitors
c15 {0-7} ‡ Reserved for IMPLEMENTATION DEFINED Performance Monitors
Read-only Read/Write
Write-only
‡ Access depends on the operation
Figure B3-21 Permitted CP15 c9 encodings
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B3-141