ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Parity error reporting
Protected Memory System Architecture (PMSA)
The ARM architecture supports the reporting of both synchronous and asynchronous parity errors from the
cache systems. It is IMPLEMENTATION DEFINED what parity errors in the cache systems, if any, result in
synchronous or asynchronous parity errors.
A fault status code is defined for reporting parity errors, see Fault Status and Fault Address registers in a
PMSA implementation on page B4-18. However when parity error reporting is implemented it is
IMPLEMENTATION DEFINED whether the assigned fault status code or another appropriate encoding is used
to report parity errors.
For all purposes other than the fault status encoding, parity errors are treated as external aborts.
B4.4.3 Prioritization of aborts
For synchronous aborts, Debug event prioritization on page C3-43 describes the relationship between debug
events, MPU faults and external aborts.
In general, the ARM architecture does not define when asynchronous events are taken, and therefore the
prioritization of asynchronous events is IMPLEMENTATION DEFINED.
Note
A special requirement applies to asynchronous watchpoints, see Debug event prioritization on page C3-43.
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