ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
The ready flag for the DBGITR, InstrCompl, is an internal flag that cannot be accessed through any
register.
For details of the ready state of each flag, and details of when the latched flags are updated, see the
descriptions of the DBGDSCR flag bits.
Different external DCC access modes require the debugger to execute different sequences of accesses to the
DBGDTRRXext and DBGDTRTXext registers, and to the DBGITR. This can affect the total number of
accesses required.
Table C10-2 shows the three external DCC access modes:
Note
Non-blocking mode is the default setting because improper use of the other modes can result in the
external debug interface becoming deadlocked.
For information that applies to all access modes see Restrictions on accesses to DBGITR,
DBGDTRRXext and DBGDTRTXext on page C10-25.
See Instruction and data transfer registers on page C10-40. The external DCC access mode field has no
effect on accesses to DBGDTRRXint and DBGDTRTXint.
Non-blocking mode
Table C10-2 Meaning of the external DCC access mode values
DBGDSCR.ExtDCCmode External DCC access mode Description
0b00 Non-blocking mode Non-blocking mode
0b01 Stall mode Stall mode on page C10-23
0b10 Fast mode Fast mode on page C10-23
When Non-blocking mode is selected, reads from DBGDTRTXext and writes to DBGDTRRXext and
DBGITR are ignored when the appropriate latched ready flag is not in the ready state:
if RXfull_l is set to 1, writes to DBGDTRRXext are ignored
if InstrCompl_l is set to 0, writes to DBGITR are ignored
if TXfull_l is set to 0, reads from DBGDTRTXext are ignored and return an UNKNOWN value.
Following a successful write to DBGDTRRXext, RXfull and RXfull_l are set to 1.
Following a successful read from DBGDTRTXext, TXfull and TXfull_l are cleared to 0.
Following a successful write to DBGITR, InstrCompl and InstrCompl_l are cleared to 0.
C10-22 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B