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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Application Level Programmers’ Model<br />

Figure A2-2 Advanced SIMD data type hierarchy<br />

For example, a multiply instruction must distinguish between integer <strong>and</strong> floating-point data types.<br />

However, some multiply instructions use modulo arithmetic for integer instructions <strong>and</strong> therefore do not<br />

need to distinguish between signed <strong>and</strong> unsigned inputs.<br />

A multiply instruction that generates a double-width (long) result must specify the input data types as signed<br />

or unsigned, because for this operation it does make a difference.<br />

A2.6.3 Advanced SIMD vectors<br />

.S8<br />

.I8<br />

.U8<br />

.P8<br />

-<br />

.S16<br />

.I16<br />

.U16<br />

.P16<br />

.F16 ‡<br />

.S32<br />

.I32<br />

.U32<br />

-<br />

.F32<br />

.S64<br />

.I64<br />

.U64<br />

-<br />

-<br />

When the Advanced SIMD extension is implemented, a register can hold one or more packed elements, all<br />

of the same size <strong>and</strong> type. The combination of a register <strong>and</strong> a data type describes a vector of elements. The<br />

vector is considered to be an array of elements of the data type specified in the instruction. The number of<br />

elements in the vector is implied by the size of the data elements <strong>and</strong> the size of the register.<br />

Vector indices are in the range 0 to (number of elements – 1). An index of 0 refers to the least significant<br />

end of the vector. Figure A2-3 on page A2-27 shows examples of Advanced SIMD vectors:<br />

A2-26 Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. <strong>ARM</strong> DDI 0406B<br />

.8<br />

.16<br />

.32<br />

.64<br />

‡ Supported only if the half-precision extensions are implemented

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