05.02.2013 Views

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

SHOW MORE
SHOW LESS

You also want an ePaper? Increase the reach of your titles

YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.

A9.4.1 LDR (register)<br />

ThumbEE<br />

Load Register (register) calculates an address from a base register value <strong>and</strong> an offset register value, loads<br />

a word from memory, <strong>and</strong> writes it to a register. The offset register value is shifted left by 2 bits. For<br />

information about memory accesses see Memory accesses on page A8-13.<br />

The similar Thumb instruction does not have a left shift.<br />

Encoding T1 ThumbEE<br />

LDR ,[,, LSL #2]<br />

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

0 1 0 1 1 0 0 Rm Rn Rt<br />

t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);<br />

Assembler syntax<br />

LDR , [, , LSL #2]<br />

where:<br />

See St<strong>and</strong>ard assembler syntax fields on page A8-7.<br />

The destination register.<br />

The base register.<br />

Contains the offset that is shifted <strong>and</strong> applied to the value of to form the address.<br />

Operation<br />

if ConditionPassed() then<br />

EncodingSpecificOperations(); NullCheckIfThumbEE(n);<br />

address = R[n] + LSL(R[m],2);<br />

R[t] = MemU[address,4];<br />

Exceptions <strong>and</strong> checks<br />

Data Abort, NullCheck.<br />

<strong>ARM</strong> DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. A9-9

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!