ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Protected Memory System Architecture (PMSA)
Fault information is returned using the fault status registers and the fault address registers described in CP15
c6, Fault Address registers on page B4-57. For details of how these registers are used see Fault Status and
Fault Address registers in a PMSA implementation on page B4-18.
c5, Data Fault Status Register (DFSR)
The Data Fault Status Register, DFSR, holds status information about the last data fault.
The DFSR is:
a 32-bit read/write register
accessible only in privileged modes.
The format of the DFSR is:
31 13 12 11 10 9
4 3 0
UNK/SBZP
UNK/SBZP
FS[3:0]
Bits [31:13,9:4]
UNK/SBZP.
ExT, bit [12] External abort type. This bit can be used to provide an IMPLEMENTATION DEFINED
classification of external aborts.
For aborts other than external aborts this bit always returns 0.
WnR, bit [11] Write not Read bit. Indicates whether the abort was caused by a write or a read access:
0 Abort caused by a read access
1 Abort caused by a write access.
FS, bits [10,3:0]
For faults on CP15 cache maintenance operations this bit always returns a value of 1.
Fault status bits. For the valid encodings of these bits in an ARMv7-R implementation with
a PMSA, see Table B4-7 on page B4-20.
All encodings not shown in the table are reserved.
For information about using the DFSR see Fault Status and Fault Address registers in a PMSA
implementation on page B4-18.
Accessing the DFSR
ExT
WnR
FS[4]
To access the DFSR you read or write the CP15 registers with set to 0, set to c5, set to
c0, and set to 0. For example:
MRC p15,0,,c5,c0,0 ; Read CP15 Data Fault Status Register
MCR p15,0,,c5,c0,0 ; Write CP15 Data Fault Status Register
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B4-55