ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
For more information about these registers see:
— c12, Vector Base Address Register (VBAR) on page B3-148
— c12, Monitor Vector Base Address Register (MVBAR) on page B3-149.
Note
The Reset exception vectors address never depends on the Vector Base Address values, and when
SCTLR.VE == 1 the IRQ and FIQ exception vector addresses do not depend on the Vector Base
Address values, see Table C10-16 on page C10-73 for more information.
Except for the Secure state vector catches on the Monitor mode vectors, on the exception vector
configuration in the SCTLR:
— whether the SCTLR.V bit is programmed for Normal or High exception vectors
— for catches on the FIQ and IRQ exception vectors, on the programming of the SCTLR.VE bit.
Generation of Vector Catch debug events also depends on the security state of the processor:
the Non-secure state vector catches are generated only in Non-secure state
the Secure state vector catches are generated only in Secure state
in v6 Debug and v6.1 Debug, Reset vector catches are generated only in Secure state.
In v7 Debug, if Reset vector catch is enabled the Reset vector catches are generated regardless of the security
state of the processor.
Generation of Vector Catch debug events takes no account of the values in the Secure Configuration
Register (SCR), except for SCR.NS. For example, if the DBGVCR is programmed to catch Secure state
IRQs on the Monitor mode vector, by setting bit [14] of the DBGVCR to 1, and the processor is in the Secure
state, a Vector Catch debug event is generated on any instruction prefetch from (MVBAR + 0x18). This
debug event is generated even if the SCR is programmed for IRQs to be handled in IRQ mode.
Table C10-15 on page C10-71 shows, for each active bit of the DBGVCR:
the security state in which the Vector Catch debug event can occur
how the corresponding vector address depends on the configuration settings.
C10-72 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B