ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

For scalar CDP instructions:
Common VFP Subarchitecture Specification
All the operand registers to the instruction are restored to their original values, so that the instruction
can be re-executed in support code.
It is IMPLEMENTATION DEFINED whether the FPEXC.VV bit is set to 1. If it is, the FPEXC.VECITR
field will contain 0b111.
If the execution of the instruction would set the cumulative exception flags for any exception,
hardware might or might not set these flags.
Note
Because the cumulative exception flags are cumulative, it is always acceptable for the support code
to set the exception flags to 1 as a result of emulating the instruction, even if the hardware has set
them.
For short vector instructions, any iteration might be exceptional. When an exceptional condition is detected
for a vector iteration, previous iterations can complete. For the exceptional iteration:
The FPEXC.VECITR field is written with a value that encodes the number of iterations remaining
after the exceptional iteration. For details of the encoding see Subarchitecture additions to the VFP
system registers on page AppxB-15.
The FPEXC.VV bit is set to 1.
The input operand registers to that iteration, and subsequent iterations, are restored to their original
values.
If the execution of the exception iteration, or subsequent iterations, would set the cumulative
exception flags for any exception, hardware might or might not set these flags.
Note
Because the cumulative exception flags are cumulative, it is always acceptable for the support code
to set the exception flags to 1 as a result of emulating the iterations of the instruction, even if the
hardware has set them.
Note
In version 1 of the Common VFP subarchitecture, all exceptions are signaled synchronously when
the FPSCR.IXE bit is set to 1, see Floating-point Status and Control Register (FPSCR) on
page A2-28. The FPEXC.DEX bit is RAZ/WI. For more information, see Subarchitecture v1
exception handling when FPSCR.IXE == 1 on page AppxB-23.
In version 2 of the Common VFP subarchitecture, exceptional conditions that cause synchronous
exceptions are signaled by setting FPEXC.DEX to 1. For more information, see Version 2 of the
Common VFP subarchitecture on page AppxB-24.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. AppxB-9