ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

C10.5.4 Watchpoint Control Registers (DBGWCR)
Debug Registers Reference
A Watchpoint Control Register, DBGWCR, holds control information for a watchpoint. Each DBGWCR is
associated with a DBGWVR to form a Watchpoint Register Pair (WRP). For more information about WRPs
and the possible watchpoints see Watchpoint Value Registers (DBGWVR) on page C10-60.
The DBGWCRs are:
debug registers 112-127, at offsets 0x1C0-0x1FC
read/write registers
when the Security Extensions are implemented, Common registers.
The format of a DBGWCR, in v7 Debug, is:
31 29 28 24 23 21 20 19 16 15 14 13 12
5 4 3 2 1 0
UNK/
SBZP
Address
range mask
See the bit descriptions for the differences in other Debug architecture versions.
Bits [31:29, 23:21,13]
UNK/
SBZP
Reserved, UNK/SBZP.
Address range mask, bits [28:24], v7 Debug
Linked
BRP num.
Byte address select
Enable linking Load/Store access control
Security state control
Privileged mode control
Watchpoint enable
In v7 Debug, support for watchpoint address range masking is optional. If it is not supported
these bits are RAZ/WI.
If watchpoint address range masking is supported, this field can be used to watch a range of
addresses by masking lower order address bits out of the watchpoint comparison. The value
of this field is the number of low order bits of the address that are masked off, except that
values of 1 and 2 are reserved. Therefore, the meaning of Watchpoint Address range mask
values are:
0b00000 No mask
0b00001 Reserved
0b00010 Reserved
0b00011 0x00000007 mask for data address, three bits masked
0b00100 0x0000000F mask for data address, four bits masked
0b00101 0x0000001F mask for data address, five bits masked
. .
. .
. .
0b11111 0x7FFFFFFF mask for data address, 31 bits masked.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C10-61
(0)