ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Application Level Programmers’ Model
The format of the JMCR is:
31 1 0
SUBARCHITECTURE DEFINED JE
bit [31:1] SUBARCHITECTURE DEFINED information.
JE, bit [0] Jazelle Enable bit:
0 Jazelle extension disabled. The BXJ instruction does not cause Jazelle state
execution. BXJ behaves exactly as a BX instruction, see Jazelle state entry
instruction, BXJ on page A2-74.
1 Jazelle extension enabled.
The reset value of this bit is 0.
To access the JMCR, read or write the CP14 registers with an MRC or MCR instruction with set to 7,
set to c2, set to c0, and set to 0. For example:
MRC p14, 7, , c2, c0, 0 ; Read Jazelle Main Configuration register
MCR p14, 7, , c2, c0, 0 ; Write Jazelle Main Configuration register
Access to Jazelle registers
Table A2-14 shows the access permissions for the Jazelle registers, and how unprivileged access to the
registers depends on the value of the JOSCR.
Jazelle register
JIDR
JMCR
SUBARCHITECTURE
DEFINED configuration
registers
Unprivileged access
JOSCR.CD == 0 a JOSCR.CD == 1 a
Table A2-14 Access to Jazelle registers
Privileged access
Read access permitted
Read and write access
Read access permitted
Write access ignored
UNDEFINED
Write access ignored
Read access UNDEFINED
Write access permitted
Read and write access
UNDEFINED
Read and write access permitted
Read access UNDEFINED
Read access SUBARCHITECTURE
Read and write access
UNDEFINED
DEFINED
Write access permitted Write access permitted
a. See Jazelle OS Control Register (JOSCR) on page B1-77.
A2-78 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B