ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The CPUID Identification Scheme
L1 Harvard range, bits [11:8]
Indicates the supported Level 1 cache maintenance range operations, for a Harvard cache
implementation. Permitted values are:
0b0000 Not supported.
0b0001 Supported Level 1 Harvard cache maintenance range operations are:
Invalidate data cache range by VA
Invalidate instruction cache range by VA
Clean data cache range by VA
Clean and invalidate data cache range by VA.
L1 Harvard bg prefetch, bits [7:4]
Indicates the supported Level 1 cache background prefetch operations, for a Harvard cache
implementation. When supported, background prefetch operations are non-blocking
operations. Permitted values are:
0b0000 Not supported.
0b0001 Supported Level 1 Harvard cache foreground prefetch operations are:
Prefetch instruction cache range by VA
Prefetch data cache range by VA.
L1 Harvard fg prefetch, bits [3:0]
Indicates the supported Level 1 cache foreground prefetch operations, for a Harvard cache
implementation. When supported, foreground prefetch operations are blocking operations.
Permitted values are:
0b0000 Not supported.
0b0001 Supported Level 1 Harvard cache foreground prefetch operations are:
Prefetch instruction cache range by VA
Prefetch data cache range by VA.
B5-16 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B