ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug state entry is the acknowledge event that clears this request.
Debug Registers Reference
Abandoned accesses have the following behavior:
an abandoned data store writes an UNKNOWN value to the target address
an abandoned data load returns an UNKNOWN value to the register bank
an abandoned instruction fetch returns an UNKNOWN instruction for execution
an abandoned cache operation leaves the memory system in an UNPREDICTABLE state.
However, an abandoned access does not cause any exception.
Additional BIU requests, after Debug state has been entered, have UNPREDICTABLE behavior.
The number of ports on the processor and their protocols are implementation specific and, therefore, the
detailed behavior of this bit is IMPLEMENTATION DEFINED. It is also IMPLEMENTATION DEFINED whether this
behavior is supported on all ports of a processor. For example, an implementation can choose not to
implement this behavior on instruction fetches.
This control bit enables the debugger to release a deadlock on the system bus so Debug state can be entered.
This Debug state entry is imprecise, because the debugger only wants to know what the state of the processor
was at the time the deadlock occurred. At the point where the deadlock is released, one of the following must
be pending:
a Halt request, made by also writing 1 to the Halt request bit of the DBGDRCR
an External Debug request.
It might not be easy to infer the cause of the deadlock by reading the PC value after entering Debug state if,
for example, either:
the processor has a non-blocking cache design or a write buffer
the deadlocked access corresponded to a load to the PC.
The effect of this bit depends on the state of the external debug interface signals:
If the processor implements Security Extensions, a write to this bit is ignored unless DBGEN and
SPIDEN are both HIGH, meaning that invasive debug is permitted in all processor states and modes.
If the processor does not implement Security Extensions, a write to this bit is ignored unless DBGEN
is HIGH.
For details of invasive debug authentication see Chapter C2 Invasive Debug Authentication.
C10.3.4 Device Power-down and Reset Control Register (DBGPRCR), v7 Debug only
The Device Power-down and Reset Control Register, DBGPRCR, controls processor functionality related
to reset and power-down.
The DBGPRCR is:
debug register 196, at offset 0x310
a read/write register, with more restricted access to some bits
implemented only in v7 Debug
when the Security Extensions are implemented, a Common register.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C10-31