ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
B3.12.39 CP15 c12, Security Extensions registers
When the Security Extensions are implemented, CP15 c12 is used for the Vector base address registers and
an Interrupt status register. Figure B3-24 shows the CP15 c12 Security Extensions registers:
CRn opc1 CRm opc2
c12 0
c0 0
1
c1
0
Figure B3-24 Security Extensions CP15 c12 registers
When the Security Extensions are implemented, CP15 c12 encodings not shown in Figure B3-24 are
UNPREDICTABLE. On an implementation that does not include the Security Extensions all CP15 c12
encodings are UNDEFINED. For more information, see Unallocated CP15 encodings on page B3-69.
The CP15 c12 registers are described in the subsections:
c12, Vector Base Address Register (VBAR)
c12, Monitor Vector Base Address Register (MVBAR) on page B3-149
c12, Interrupt Status Register (ISR) on page B3-150.
B3.12.40 c12, Vector Base Address Register (VBAR)
When the Security Extensions are implemented and high exception vectors are not selected, the Vector Base
Address Register, VBAR, provides the exception base address for exceptions that are not handled in Monitor
mode, see Exception vectors and the exception base address on page B1-30. The high exception vectors
always have the base address 0xFFFF0000 and are not affected by the value of VBAR.
The VBAR:
Read-only Read/Write
Write-only
* Implemented only when the Security Extensions are implemented
Is present only when the Security Extensions are implemented.
Is a 32-bit read/write register.
Is accessible only in privileged modes.
Has a defined reset value, for the Secure copy of the register, of 0. This reset value does not apply to
the Non-secure copy of the register, and software must program the Non-secure copy of the register
with the required value, as part of the processor boot sequence.
Is a Banked register.
* VBAR, Vector Base Address Register
* MVBAR, Monitor Vector Base Address Register
* ISR, Interrupt Status Register
Has write access to the Secure copy of the register disabled when the CP15SDISABLE signal is
asserted HIGH.
B3-148 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B