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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Cache contention<br />

Is when the number of frequently-used memory cache lines that use a particular cache set exceeds the<br />

set-associativity of the cache. In this case, main memory activity goes up <strong>and</strong> performance drops.<br />

Glossary<br />

Cache hit<br />

Is a memory access that can be processed at high speed because the data it addresses is already in the cache.<br />

Cache line<br />

Is the basic unit of storage in a cache. Its size is always a power of two (usually 4 or 8 words), <strong>and</strong> must be<br />

aligned to a suitable memory boundary. A memory cache line is a block of memory locations with the same<br />

size <strong>and</strong> alignment as a cache line. Memory cache lines are sometimes loosely just called cache lines.<br />

Cache line index<br />

Is a number associated with each cache line in a cache set. In each cache set, the cache lines are numbered<br />

from 0 to (set associativity)–1.<br />

Cache lockdown<br />

Alleviates the delays caused by accessing a cache in a worst-case situation. Cache lockdown enables critical<br />

code <strong>and</strong> data to be loaded into the cache so that the cache lines containing them are not subsequently<br />

re-allocated. This ensures that all subsequent accesses to the code <strong>and</strong> data concerned are cache hits <strong>and</strong> so<br />

complete quickly.<br />

Cache lockdown blocks<br />

Consist of one line from each cache set. Cache lockdown is performed in units of a cache lockdown block.<br />

Cache miss<br />

Is a memory access that cannot be processed at high speed because the data it addresses is not in the cache.<br />

Cache sets<br />

Are areas of a cache, divided up to simplify <strong>and</strong> speed up the process of determining whether a cache hit<br />

occurs. The number of cache sets is always a power of two.<br />

Cache way<br />

A cache way consists of one cache line from each cache set. The cache ways are indexed from 0 to<br />

ASSOCIATIVITY-1. The cache lines in a cache way are chosen to have the same index as the cache way.<br />

So for example cache way 0 consists of the cache line with index 0 from each cache set, <strong>and</strong> cache way n<br />

consists of the cache line with index n from each cache set.<br />

Callee-save registers<br />

Are registers that a called procedure must preserve. To preserve a callee-save register, the called procedure<br />

would normally either not use the register at all, or store the register to the stack during procedure entry <strong>and</strong><br />

re-load it from the stack during procedure exit.<br />

Caller-save registers<br />

Are registers that a called procedure need not preserve. If the calling procedure requires their values to be<br />

preserved, it must store <strong>and</strong> reload them itself.<br />

Condition field<br />

Is a 4-bit field in an instruction that is used to specify a condition under which the instruction can execute.<br />

<strong>ARM</strong> DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. Glossary-3

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