ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Protected Memory System Architecture (PMSA)
Figure B4-1 shows a case where the MPU is programmed with overlapping memory regions.
In this example:
Figure B4-1 Overlapping memory regions in the MPU
Data region 2 is programmed to be 4KB in size, starting from address 0x3000 with AP[2:0} == 0b010,
giving privileged mode full access, User mode read-only access.
Data region 1 is programmed to be 16KB in size, starting from address 0x0 with AP[2:0} == 0b001,
giving privileged mode access only.
If the processor performs a data load from address 0x3010 while in User mode, the address is in both region 1
and region 2. Region 2 has the higher priority, therefore the region 2 attributes apply to the access. This
means the load does not abort.
B4.1.4 The background region
0x3010
0x4000
0x3000
0x0000
Region 2
Region 1
Background region refers to a region that matches the entire 4GB physical address map, and has a lower
priority than any other region. Therefore, a background region provides the memory attributes for any
memory access that does not match any of the defined memory regions.
When the SCTLR.BR bit is set to 0, the MPU behaves as if there is a background region that generates a
Background Fault memory abort on any access. This means that any memory access that does not match
any of the programmed memory regions generates a Background Fault memory abort. This is the same as
the behavior in PMSAv6.
If you want a background region with a different set of memory attributes, you can program region 0 as a
4GB region with the attributes you require. Because region 0 has the lowest priority this region then acts as
a background region.
B4-4 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B