ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
F, bit [7] Fast interrupt pending flag. Indicates whether an FIQ fast interrupt is pending:
0 no pending FIQ
1 an FIQ fast interrupt is pending.
Bits [5:0] Reserved, UNK/SBZP.
The bit positions of the A, I and F flags in the ISR match the A, I and F flag bits in the CPSR, see Program
Status Registers (PSRs) on page B1-14. This means the same masks can be used to extract the flags from
the register value.
Note
The ISR.F and ISR.I bits directly reflect the state of the FIQ and IRQ inputs.
the ISR.A bit is set when an asynchronous abort is generated and is cleared automatically when the
abort is taken.
Accessing the ISR
To access the ISR you read the CP15 registers with set to 0, set to c12, set to c1, and
set to 0. For example:
MRC p15,0,,c12,c1,0 ; Read Interrupt Status Register
B3.12.43 CP15 c13, Process, context and thread ID registers
The CP15 c13 registers are used for:
a Context ID register
three software Thread ID registers
an FCSE Process ID Register.
Note
From ARMv6, use of the FCSE is a deprecated, and in ARMv7 the FCSE is an optional component of a
VMSA implementation. ARM expects the FCSE will become obsolete during the lifetime of ARMv7.
However, every ARMv7-A implementation must include the FCSE Process ID Register.
Figure B3-25 on page B3-152 shows the CP15 c13 registers:
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B3-151