ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
RFE{} {!}
where:
is one of:
System Instructions
DA Decrement After. ARM code only. The consecutive memory addresses end at
the address in the base register. Encoded as P = 0, U = 0 in encoding A1.
DB Decrement Before. The consecutive memory addresses end one word below the
address in the base register. Encoding T1, or encoding A1 with P = 1, U = 0.
IA Increment After. The consecutive memory addresses start at the address in the
base register. This is the default, and is normally omitted. Encoding T2, or
encoding A1 with P = 0, U = 1.
IB Increment Before. ARM code only. The consecutive memory addresses start
one word above the address in the base register. Encoded as P = 1, U = 1 in
encoding A1.
See Standard assembler syntax fields on page A8-7. An ARM RFE instruction must be
unconditional.
The base register.
! Causes the instruction to write a modified value back to . If ! is omitted, the instruction
does not change .
RFEFA, RFEEA, RFEFD, and RFEED are pseudo-instructions for RFEDA, RFEDB, RFEIA, and RFEIB respectively,
referring to their use for popping data from Full Ascending, Empty Ascending, Full Descending, and Empty
Descending stacks.
Operation
if ConditionPassed() then
EncodingSpecificOperations();
if !CurrentModeIsPrivileged() || CurrentInstrSet() == InstrSet_ThumbEE then
UNPREDICTABLE;
else
address = if increment then R[n] else R[n]-8;
if wordhigher then address = address+4;
CPSRWriteByInstr(MemA[address+4,4], ‘1111’, TRUE);
BranchWritePC(MemA[address,4]);
if wback then R[n] = if increment then R[n]+8 else R[n]-8;
Exceptions
Data Abort.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B6-17